The present application relates to the fabrication of semiconductor devices, and more particularly to the formation of a stacked nanowire complementary metal oxide semiconductor (CMOS) device.
The use of non-planar semiconductor devices such as, for example, semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor nanowire FETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Three-dimensional (3D) monolithic integration by stacking one type of FETs (e.g., p-type FETs) on top of a complementary type of FETs (e.g., n-type FETs) is an attractive approach for 5 nm node technology and beyond. FET stacking combined with nanowire technology can benefit from device electrostatics control in addition to area scaling. Despite the above advantages in 3D monolithic integration, FET stacking approaches usually require complicated fabrication processes. In addition, such vertical device architecture also makes the formation of contact structures for the vertically stacked FETs very difficult. There remains a challenge in forming 3D stacked transistors as well as contact structures to such 3D stacked transistors.